(1) Field of the Invention
The invention relates to a method and system to reduce clock noise in a multiple clock circuit, and, more particularly, to a method and system to reduce clock noise caused by frequency sum and difference components using a spectral energy spreading technique.
(2) Description of the Prior Art
In the art of integrated circuits, clock signals are used to time or synchronize circuit operators. Sometimes more than one clock signal frequency must be used in the circuit. In such cases, the circuit is said to be a multiple clock circuit. Referring now to FIG. 1, an example of multiple clock integrated circuit is shown. In this example, the integrated circuit device 10 is a mixed signal IC. In a mixed signal IC, analog and digital circuits are integrated in a common, system on chip (SOC) approach. The circuit has a set of inputs (IN) 14 and a set of outputs (OUT) 18.
Two clock signals, CLK122 and CLK 26, are used on the circuit device 10. While the two clocks are shown as externally accessible, these clock signals may be only internally available. Further, CLK122 and CLK226 comprise different frequencies, f1 and f2. It is known in the art that, if cyclical signals interact, or couple, then this interaction can create signals having frequencies that are related to the original signals. In particular, clock signals CLK1 and CLK2 can interact to create unwanted, or noise, signals at the frequencies represented by the sum and difference of the original frequencies. More specifically, the interaction of CLK1 and CLK2 will create noise components at fNOISE1=f1+f2, and fNOISE1=f1xe2x88x92f2. The spectral energy of the clock signals f1 32 and f2 36 is shown in FIG. 1. In addition, the spectral energy of the noise products at f1xe2x88x92f2 40 and f1xe2x88x92f2 44 are shown.
In practice, when multiple clock frequencies are used on a single device 10, attempts are made to isolate the clock signals one from another. For example, separate power and ground routings and/or separate power and ground external connections may be used to isolate circuit sections having different clock frequencies. In addition, the CLK1 and CLK2 areas may be separated by physical layout distance to reduce capacitance coupling effects. However, the fact that the device 10 of the example is a mixed signal circuit makes the problem more difficult to solve. Digital circuits typically can operate successfully in the presence of relatively large clock switching noise. However, analog circuits, by nature, can be very sensitive to noise. For example, an analog-to-digital converter circuit may not function properly in the presence of as little as 4 millivolts of substrate noise. Traditional layout and routing techniques may not adequately reduce clock interaction, and, therefore, spectral combination noise may still occur. In addition, these approaches use precious I/O pins and layout area.
Referring now to FIG. 2, a particular mixed signal device example is shown. In this example, a liquid crystal display (LCD) controller 50 is shown. The LCD controller 50 is used to convert an analog video signal 62, here comprising the red-green-blue (RGB) analog video from a PC video card 54, into a digital RGB video signal 64 to drive a LCD panel 58. In this situation, the LCD controller 50 performs two critical functions. First, the analog video signal 62 must be converted into a digital signal using the analog input section 68 of the device 50. Second, the analog video input 62 from the video card 54 may be configured to any of several different resolutions for XGA, SVGA, or VGA formats. For example, the PC video card may be configured to source 1024xc3x97768 pixels or to source 800xc3x97600 pixels. Many other screen formats could be configured. However, the LCD panel 58 is a fixed resolution device. Therefore, the second function of the LCD controller 50 is to map, or scale, the variable resolution video input 62 to a fixed resolution output 64.
To perform the major functions of analog-to-digital conversion (ADC) and scaling, the LCD controller 50 is designed as an analog section 68 and a digital scaling section 72. While the ADC is essentially an analog device, a first clock signal CLK174 is used to control when the analog video signals (RGB) 62 are sampled. CLK174 is derived from a horizontal synchronization signal (HSYNC) that indicates the beginning of each horizontal line of video data. Typically, CLK174 is derived from HSYNC using a phase lock loop circuit (PLL) and has a frequency of M times the HSYNC frequency where M is the number of pixels per horizontal line of data.
After the analog video data 62 is converted to a stream of digital data by the ADC section 68, this digital data must be scaled to the fixed output resolution. For example, an input resolution of 800 pixels per line may have to be scaled to a fixed output resolution of 1024 pixels per line. To execute the scaling function, a digital scaling section 72 uses a second clock signal CLK276. CLK276 must also be derived, or synchronized, to HSYNC but at a different frequency than that used for CLK174. CLK276 is then used by the LCD panel 58 to synchronize the data stream output 64.
The combination of CLK174 and CLK276 on the mixed signal, LCD controller 50 presents a potentially troublesome noise situation. Once again, the coupling of the clock signals can cause additional frequency components at the sum and difference frequencies. In particular, the difference noise component, f1xe2x88x92f2, can couple into the ADC section 68. This noise component shows up in the LCD panel 58 display data as visible noise lines 80. These noise lines 80 are undesirable and need to be eliminated.
Several prior art inventions relate to methods and circuits for reducing clock noise on a device. U.S. Pat. No. 6,232,905 to Smith et al discloses a clocking technique to reduce sampling noise in an analog-to-digital converter (ADC). The technique uses a clean, low frequency clock to disable the ADC sample rather than using the noisy, phase lock loop (PLL) derived clock. U.S. Pat. No. 6,215,423 to May et al describes a method and a system for asynchronous sample rate conversion using a noise-shaped, numerically controlled oscillator. The oscillator generates a clock that is synchronous to the system clock but that has a time average frequency that is equal to a multiple of the asynchronous sampling rate. Unwanted spectral energy is noise-shaped out of the passband. No PLL is used. U.S. Pat. No. 5,731,737 to Cranford, Jr. et al teaches a method and a system to reduce clock-switching noise in a continuous time filter.
A principal object of the present invention is to provide an effective and very manufacturable method and system for reducing clock noise in a multiple clock system.
A further object of the present invention is to provide a method and system to reduce harmonic, frequency sum and difference noise in a multiple clock system.
A yet further object of the present invention is to reduce noise by spreading the spectral energy of a clock signal to thereby spread the spectral energy of the sum and difference components.
A still yet further object of the present invention is to derive a clock having a frequency that is a non-constant multiple of a periodic signal where the non-constant multiple is a sum of a constant value and a time varying value.
Another still yet further object of the present invention is to derive a clock having a non-constant multiple frequency of a periodic signal by using a phase lock loop (PLL) circuit.
Another further object of the present invention is to provide a clock reduction method and system for a LCD controller device particularly as it relates to the conversion of analog video to digital video.
In accordance with the objects of this invention, a method to reduce clock noise in a multiple clock circuit is achieved. The method comprises, first, providing a periodic signal. Next, a first clock signal is provided having a frequency that is a constant multiple of the frequency of the periodic signal. Finally, a second clock signal is derived from the periodic signal. The second clock signal has a frequency that is a non-constant multiple of the periodic signal frequency. The non-constant multiple comprises the sum of a constant value plus a time-varying value. The spectral energy at the sum and difference frequencies of the first and second clock signals is reduced by frequency distribution spreading.
Also in accordance with the objects of this invention, a multiple clock generating circuit having reduced clock noise is achieved. The circuit comprises, first, a means of deriving a first clock signal from a periodic signal. The first clock signal has a frequency that is a constant multiple of the frequency of the periodic signal. Second, a phase lock loop issued for deriving a second clock signal from the periodic signal. The second clock signal has a frequency that is a non-constant multiple of the periodic signal frequency. The non-constant multiple comprises the sum of a constant value plus a time-varying value. The spectral energy at the sum and difference frequencies of the first and second clock signals is reduced by frequency distribution spreading.